perf(rt): allocate TLAS instance buffer in BAR/VRAM, not system RAM (#65) #105

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catbot merged 1 commit from claude/issue-65 into master

2026-06-17 19:38:14 +02:00

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2026-06-17 19:38:09 +02:00

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Summary

The TLAS instance buffer is rebuilt/refit every frame and is co-written by both CPU and GPU: the compute shader writes the transform field in place for transformOwnedByGpu elements, and the CPU loop writes the other fields. Allocated HOST_VISIBLE | HOST_COHERENT (system RAM), both GPU accesses crossed PCIe — the compute write of the transform, and the AS build's read of the whole instance.

This upgrades the request to HOST_VISIBLE with a best-effort DEVICE_LOCAL preference (BAR/VRAM), keeping the single shared, persistently-mapped buffer. No staging, no copy, no extra barrier:

GPU compute writes the transform → local VRAM (was PCIe).
AS build reads instances → local VRAM (was PCIe).
CPU writes host-authored fields → write-only, sequential, never-read-back writes into write-combined BAR (the ideal WC workload).

A whole-buffer staging copy was deliberately not used: it would clobber the GPU-written transforms in this in-place co-write design.

Correctness

Prefer-but-require (depends on #59): GetMemoryType falls back to plain HOST_VISIBLE (the previous behaviour) on GPUs without resizable BAR.
HOST_COHERENT dropped from the required set — the combined type may not be coherent. The existing FlushDevice(cmd, ...) already establishes host→build visibility and gates its flush-skip on the chosen type's flags (#60), so a non-coherent BAR type still flushes correctly. The barrier is never removed.
BAR-window pressure is negligible: primitiveCount × 64 B ≈ 6 MB even at 100k instances.
metadataBuffer gets the same upgrade separately in #75.

Testing

crafter-build test — 19/19 pass. The TLASHighWaterMark hardware test (real RT device + validation layers) is extended to assert the instance buffer's chosen memory type matches the HOST_VISIBLE | prefer-DEVICE_LOCAL request and lands on a DEVICE_LOCAL type where one is reachable. Confirmed on the test GPU: the buffer is now placed in a DEVICE_LOCAL BAR type with zero validation errors (the latter covers the dropped-HOST_COHERENT flush path).

Resolves #65

🤖 Generated with Claude Code

## Summary The TLAS instance buffer is rebuilt/refit **every frame** and is co-written by both CPU and GPU: the compute shader writes the transform field in place for `transformOwnedByGpu` elements, and the CPU loop writes the other fields. Allocated `HOST_VISIBLE | HOST_COHERENT` (system RAM), **both** GPU accesses crossed PCIe — the compute write of the transform, and the AS build's read of the whole instance. This upgrades the request to `HOST_VISIBLE` with a best-effort `DEVICE_LOCAL` preference (BAR/VRAM), keeping the single shared, persistently-mapped buffer. No staging, no copy, no extra barrier: - GPU compute writes the transform → local VRAM (was PCIe). - AS build reads instances → local VRAM (was PCIe). - CPU writes host-authored fields → write-only, sequential, never-read-back writes into write-combined BAR (the ideal WC workload). A whole-buffer staging copy was deliberately **not** used: it would clobber the GPU-written transforms in this in-place co-write design. ## Correctness - **Prefer-but-require** (depends on #59): `GetMemoryType` falls back to plain `HOST_VISIBLE` (the previous behaviour) on GPUs without resizable BAR. - **`HOST_COHERENT` dropped** from the required set — the combined type may not be coherent. The existing `FlushDevice(cmd, ...)` already establishes host→build visibility and gates its flush-skip on the *chosen* type's flags (#60), so a non-coherent BAR type still flushes correctly. The barrier is never removed. - BAR-window pressure is negligible: `primitiveCount × 64 B` ≈ 6 MB even at 100k instances. - `metadataBuffer` gets the same upgrade separately in #75. ## Testing `crafter-build test` — 19/19 pass. The `TLASHighWaterMark` hardware test (real RT device + validation layers) is extended to assert the instance buffer's chosen memory type matches the `HOST_VISIBLE | prefer-DEVICE_LOCAL` request and lands on a `DEVICE_LOCAL` type where one is reachable. Confirmed on the test GPU: the buffer is now placed in a `DEVICE_LOCAL` BAR type with zero validation errors (the latter covers the dropped-`HOST_COHERENT` flush path). Resolves #65 🤖 Generated with [Claude Code](https://claude.com/claude-code)

catbot added 1 commit

2026-06-17 19:38:09 +02:00

perf(rt): allocate TLAS instance buffer in BAR/VRAM, not system RAM (#65 ) d8bc8a4e45

The TLAS instance buffer is rebuilt/refit every frame and is co-written by
both the CPU (host-authored fields) and the GPU (the compute shader writes
the transform field in place for transformOwnedByGpu elements). Allocated
HOST_VISIBLE | HOST_COHERENT (system RAM), both GPU accesses crossed PCIe:
the compute write of the transform, and the AS build's read of the instances.

Upgrade the request to HOST_VISIBLE with a best-effort DEVICE_LOCAL preference
(BAR/VRAM), keeping the single shared, persistently-mapped buffer — no staging,
no copy, no extra barrier. A whole-buffer staging copy was rejected: it would
clobber the GPU-written transforms in this in-place co-write design. Now the
compute write and AS build stay in local VRAM; the CPU's write-only,
sequential, never-read-back field writes are the ideal write-combined BAR load.

Correctness:
- DEVICE_LOCAL is a preference only (depends on #59): GetMemoryType falls back
  to plain HOST_VISIBLE (the previous behaviour) on GPUs without resizable BAR.
- HOST_COHERENT is dropped from the required set — the combined type may not be
  coherent. The existing FlushDevice(cmd, ...) already establishes host->build
  visibility and gates its flush-skip on the *chosen* type's flags (#60), so a
  non-coherent BAR type still flushes correctly. The barrier is never removed.

metadataBuffer gets the same upgrade separately (#75).

Extends the TLASHighWaterMark hardware test to assert the chosen memory type
matches the HOST_VISIBLE | prefer-DEVICE_LOCAL request and lands on a
DEVICE_LOCAL type where one is reachable; the existing zero-validation-errors
check covers the dropped HOST_COHERENT path.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

catbot merged commit 576a5eb717 into master

2026-06-17 19:38:14 +02:00

catbot deleted branch claude/issue-65

2026-06-17 19:38:14 +02:00

catbot referenced this pull request from a commit

2026-06-17 19:38:15 +02:00

Merge pull request 'perf(rt): allocate TLAS instance buffer in BAR/VRAM, not system RAM (#65)' (#105) from claude/issue-65 into master