Jorijn van der Graaf
0c55e76873
NEON backend for VectorF32 on AArch64: one float32x4_t per vector (Len * Packing <= 4), with a vectorised sin/cos port of the SSE helpers. VectorF16 gets a native float16x8_t path when the target has ARMv8.2-FP16 arithmetic. Without it VectorF16 aliases VectorF32, which converts fp16 <-> fp32 on Load/Store. The scalar fallback gains the batched Dot that MatrixRowMajor relies on. Test tiers added for armv8-a and armv8.2-a+fp16. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
68 lines
2.6 KiB
C++
68 lines
2.6 KiB
C++
//SPDX-License-Identifier: LGPL-3.0-only
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//SPDX-FileCopyrightText: Copyright (C) 2026 Catcrafts®
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import std;
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import Crafter.Build;
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namespace fs = std::filesystem;
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using namespace Crafter;
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extern "C" Configuration CrafterBuildProject(std::span<const std::string_view> args) {
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std::array<fs::path, 8> mathInterfaces = {
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"interfaces/Crafter.Math-Basic",
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"interfaces/Crafter.Math",
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"interfaces/Crafter.Math-Common",
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"interfaces/Crafter.Math-Vector",
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"interfaces/Crafter.Math-Intersection",
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"interfaces/Crafter.Math-MatrixRowMajor",
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"interfaces/Crafter.Math-VectorF16",
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"interfaces/Crafter.Math-VectorF32",
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};
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Configuration cfg;
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cfg.path = "./";
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cfg.name = "Crafter.Math";
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cfg.outputName = "Crafter.Math";
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cfg.type = ConfigurationType::LibraryStatic;
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ApplyStandardArgs(cfg, args);
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{
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std::array<fs::path, 0> impls = {};
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cfg.GetInterfacesAndImplementations(mathInterfaces, impls);
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}
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// SIMD tier matrix: each tier rebuilds the math interfaces with its own
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// -march so codegen actually varies. Per-arch gating is just an `if`
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// around the AddMarchVariants call.
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std::array<MarchTier, 3> x86Tiers = {{
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{"sapphirerapids", "native"},
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{"x86-64-v4", "generic"},
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{"x86-64-v3", "generic"},
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}};
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// RISC-V tiers mirror the x86 selector: register width is picked from
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// the guaranteed VLEN encoded in the march's Zvl* suffix. rv64gcv →
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// ZVL128B (matches the RVA23 baseline).
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std::array<MarchTier, 3> riscvTiers = {{
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{"rv64gcv_zvl512b", "generic"},
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{"rv64gcv_zvl256b", "generic"},
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{"rv64gcv", "generic"},
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}};
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// AArch64 has a single NEON register width (128-bit), so the tiers
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// differ in VectorF16 only: ARMv8.2-FP16 gives it a native half-precision
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// path, the baseline aliases it to VectorF32.
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std::array<MarchTier, 2> armTiers = {{
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{"armv8.2-a+fp16", "generic"},
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{"armv8-a", "generic"},
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}};
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const std::string_view target = cfg.target;
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const bool isX86 = target.starts_with("x86_64") || target.starts_with("i686");
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const bool isRiscv = target.starts_with("riscv");
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const bool isArm = target.starts_with("aarch64");
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for (std::string_view name : { "Vector", "Intersection", "Matrix" }) {
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if (isX86) cfg.AddMarchVariants(name, mathInterfaces, x86Tiers);
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if (isRiscv) cfg.AddMarchVariants(name, mathInterfaces, riscvTiers);
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if (isArm) cfg.AddMarchVariants(name, mathInterfaces, armTiers);
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}
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return cfg;
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}
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