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FROMGIT drm/msm/a8xx: Fix RSCC offset

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In A8xx, the RSCC block is part of GPU's register space. Update the
virtual base address of rscc to point to the correct address.

Fixes: 50e8a557d8 ("drm/msm/a8xx: Add support for A8x GMU")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/727117/
Message-ID: <20260522-glymur-gpu-dt-v5-1-562c406b210c@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
This commit is contained in:
Akhil P Oommen 2026-05-22 15:41:57 +05:30 • committed by Luca Weiss
commit 00fbf5077f
1 changed files with 6 additions and 1 deletions
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7
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
View file

@ -2401,7 +2401,12 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
goto err_mmio;
}
} else if (adreno_is_a8xx(adreno_gpu)) {
gmu->rscc = gmu->mmio + 0x19000;
/*
* On a8xx , RSCC lives at GPU base + 0x50000, which falls
* inside the GPU's kgsl_3d0_reg_memory range rather than the
* GMU's.
*/
gmu->rscc = gpu->mmio + 0x50000;
} else {
gmu->rscc = gmu->mmio + 0x23000;
}