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octeontx2-af: npc: Fix CPT channel mask in npc_install_flow

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Use the CPT-aware NIX channel mask in the npc_install_flow path so that
when the host PF installs steering rules in kernel for a VF used from
userspace (e.g. DPDK), MCAM entries see the same channel mask semantics as
other RX paths.

Fixes: 56bcef528b ("octeontx2-af: Use npc_install_flow API for promisc and broadcast entries")
Cc: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com>
Link: https://patch.msgid.link/20260602045853.1558530-1-rkannoth@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Nithin Dabilpuram 2026-06-02 10:28:53 +05:30 • committed by Jakub Kicinski
commit 1d31eb27e5
3 changed files with 18 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

1
drivers/net/ethernet/marvell/octeontx2/af/rvu.h
View file

@ -1145,6 +1145,7 @@ int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf,
int slot);
int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc);
int rvu_cpt_init(struct rvu *rvu);
u32 rvu_get_cpt_chan_mask(struct rvu *rvu);
#define NDC_AF_BANK_MASK GENMASK_ULL(7, 0)
#define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16)

32
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
View file

@ -701,6 +701,19 @@ void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
return rvu_write64(rvu, blkaddr, reg, cfg);
}
u32 rvu_get_cpt_chan_mask(struct rvu *rvu)
{
/* For cn10k the upper two bits of the channel number are
* cpt channel number. with masking out these bits in the
* mcam entry, same entry used for NIX will allow packets
* received from cpt for parsing.
*/
if (!is_rvu_otx2(rvu))
return NIX_CHAN_CPT_X2P_MASK;
else
return 0xFFFu;
}
void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
int nixlf, u64 chan, u8 *mac_addr)
{
@ -750,7 +763,7 @@ void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
eth_broadcast_addr((u8 *)&req.mask.dmac);
req.features = BIT_ULL(NPC_DMAC);
req.channel = chan;
req.chan_mask = 0xFFFU;
req.chan_mask = rvu_get_cpt_chan_mask(rvu);
req.intf = pfvf->nix_rx_intf;
req.op = action.op;
req.hdr.pcifunc = 0; /* AF is requester */
@ -845,11 +858,7 @@ void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
* mcam entry, same entry used for NIX will allow packets
* received from cpt for parsing.
*/
if (!is_rvu_otx2(rvu)) {
req.chan_mask = NIX_CHAN_CPT_X2P_MASK;
} else {
req.chan_mask = 0xFFFU;
}
req.chan_mask = rvu_get_cpt_chan_mask(rvu);
if (chan_cnt > 1) {
if (!is_power_of_2(chan_cnt)) {
@ -1053,16 +1062,7 @@ void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
ether_addr_copy(req.mask.dmac, mac_addr);
req.features = BIT_ULL(NPC_DMAC);
/* For cn10k the upper two bits of the channel number are
* cpt channel number. with masking out these bits in the
* mcam entry, same entry used for NIX will allow packets
* received from cpt for parsing.
*/
if (!is_rvu_otx2(rvu))
req.chan_mask = NIX_CHAN_CPT_X2P_MASK;
else
req.chan_mask = 0xFFFU;
req.chan_mask = rvu_get_cpt_chan_mask(rvu);
req.channel = chan;
req.intf = pfvf->nix_rx_intf;
req.entry = index;

2
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c
View file

@ -1820,7 +1820,7 @@ process_flow:
/* ignore chan_mask in case pf func is not AF, revisit later */
if (!is_pffunc_af(req->hdr.pcifunc))
req->chan_mask = 0xFFF;
req->chan_mask = rvu_get_cpt_chan_mask(rvu);
err = npc_check_unsupported_flows(rvu, req->features, req->intf);
if (err) {