From 2c0dbc3bd634f0ed8c0572e689e264d02e6f1609 Mon Sep 17 00:00:00 2001 From: Jorijn van der Graaf Date: Wed, 8 Jul 2026 22:56:00 +0200 Subject: [PATCH] TEST: milos/fp6: enable SEN_MI2S bclk control (Rafi clock series experiment) Wire the FP6's SENARY_MI2S_RX dai to the q6prm SEN_MI2S_IBIT clock via the new dai@ subnode binding, and set mi2s_bclk_enable in the milos board data so the machine driver votes the bit clock at hw_params. Experiment: does the IBIT vote alone put BCLK on the wire before GRAPH_START, satisfying aw88261's synchronous power-up clock check? The prepare-start carry is reverted on this branch; if audio works, the vendor clock series replaces our q6apm-prepare RFC. --- arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 11 +++++++++++ sound/soc/qcom/sc8280xp.c | 1 + 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts index 35c17f7c11ea..2e90892cbc1f 100644 --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -1018,6 +1018,17 @@ status = "okay"; }; +&q6apmbedai { + #address-cells = <1>; + #size-cells = <0>; + + dai@147 { + reg = ; + clocks = <&q6prmcc LPASS_CLK_ID_SEN_MI2S_IBIT LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "bclk"; + }; +}; + &qup_uart11_cts { /* * Configure a bias-bus-hold on CTS to lower power diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c index 1c25ea282a48..9546d9233d9b 100644 --- a/sound/soc/qcom/sc8280xp.c +++ b/sound/soc/qcom/sc8280xp.c @@ -304,6 +304,7 @@ static struct snd_soc_common milos_priv_data = { .driver_name = "milos", .dapm_widgets = sc8280xp_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), + .mi2s_bclk_enable = true, .wcd_jack = true, };