riscv: move the XOR code to lib/raid/
Move the optimized XOR into lib/raid and include it it in xor.ko instead of always building it into the main kernel image. Link: https://lkml.kernel.org/r/20260327061704.3707577-17-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Eric Biggers <ebiggers@kernel.org> Tested-by: Eric Biggers <ebiggers@kernel.org> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexander Gordeev <agordeev@linux.ibm.com> Cc: Alexandre Ghiti <alex@ghiti.fr> Cc: Andreas Larsson <andreas@gaisler.com> Cc: Anton Ivanov <anton.ivanov@cambridgegreys.com> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Borislav Petkov (AMD)" <bp@alien8.de> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Mason <clm@fb.com> Cc: Christian Borntraeger <borntraeger@linux.ibm.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: David S. Miller <davem@davemloft.net> Cc: David Sterba <dsterba@suse.com> Cc: Heiko Carstens <hca@linux.ibm.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Huacai Chen <chenhuacai@kernel.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jason A. Donenfeld <jason@zx2c4.com> Cc: Johannes Berg <johannes@sipsolutions.net> Cc: Li Nan <linan122@huawei.com> Cc: Madhavan Srinivasan <maddy@linux.ibm.com> Cc: Magnus Lindholm <linmag7@gmail.com> Cc: Matt Turner <mattst88@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Richard Henderson <richard.henderson@linaro.org> Cc: Richard Weinberger <richard@nod.at> Cc: Russell King <linux@armlinux.org.uk> Cc: Song Liu <song@kernel.org> Cc: Sven Schnelle <svens@linux.ibm.com> Cc: Ted Ts'o <tytso@mit.edu> Cc: Vasily Gorbik <gor@linux.ibm.com> Cc: WANG Xuerui <kernel@xen0n.name> Cc: Will Deacon <will@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
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5 changed files with 59 additions and 57 deletions
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@ -17,6 +17,7 @@ xor-$(CONFIG_ARM64) += arm64/xor-neon.o arm64/xor-neon-glue.o
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xor-$(CONFIG_CPU_HAS_LSX) += loongarch/xor_simd.o
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xor-$(CONFIG_CPU_HAS_LSX) += loongarch/xor_simd_glue.o
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xor-$(CONFIG_ALTIVEC) += powerpc/xor_vmx.o powerpc/xor_vmx_glue.o
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xor-$(CONFIG_RISCV_ISA_V) += riscv/xor.o riscv/xor-glue.o
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CFLAGS_arm/xor-neon.o += $(CC_FLAGS_FPU)
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56
lib/raid/xor/riscv/xor-glue.c
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56
lib/raid/xor/riscv/xor-glue.c
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@ -0,0 +1,56 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2021 SiFive
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*/
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#include <linux/raid/xor_impl.h>
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#include <asm/vector.h>
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#include <asm/switch_to.h>
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#include <asm/asm-prototypes.h>
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#include <asm/xor.h>
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static void xor_vector_2(unsigned long bytes, unsigned long *__restrict p1,
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const unsigned long *__restrict p2)
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{
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kernel_vector_begin();
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xor_regs_2_(bytes, p1, p2);
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kernel_vector_end();
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}
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static void xor_vector_3(unsigned long bytes, unsigned long *__restrict p1,
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const unsigned long *__restrict p2,
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const unsigned long *__restrict p3)
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{
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kernel_vector_begin();
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xor_regs_3_(bytes, p1, p2, p3);
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kernel_vector_end();
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}
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static void xor_vector_4(unsigned long bytes, unsigned long *__restrict p1,
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const unsigned long *__restrict p2,
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const unsigned long *__restrict p3,
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const unsigned long *__restrict p4)
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{
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kernel_vector_begin();
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xor_regs_4_(bytes, p1, p2, p3, p4);
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kernel_vector_end();
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}
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static void xor_vector_5(unsigned long bytes, unsigned long *__restrict p1,
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const unsigned long *__restrict p2,
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const unsigned long *__restrict p3,
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const unsigned long *__restrict p4,
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const unsigned long *__restrict p5)
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{
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kernel_vector_begin();
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xor_regs_5_(bytes, p1, p2, p3, p4, p5);
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kernel_vector_end();
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}
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struct xor_block_template xor_block_rvv = {
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.name = "rvv",
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.do_2 = xor_vector_2,
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.do_3 = xor_vector_3,
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.do_4 = xor_vector_4,
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.do_5 = xor_vector_5
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};
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77
lib/raid/xor/riscv/xor.S
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77
lib/raid/xor/riscv/xor.S
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@ -0,0 +1,77 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2021 SiFive
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*/
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#include <linux/linkage.h>
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#include <linux/export.h>
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#include <asm/asm.h>
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SYM_FUNC_START(xor_regs_2_)
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vsetvli a3, a0, e8, m8, ta, ma
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vle8.v v0, (a1)
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vle8.v v8, (a2)
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sub a0, a0, a3
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vxor.vv v16, v0, v8
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add a2, a2, a3
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vse8.v v16, (a1)
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add a1, a1, a3
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bnez a0, xor_regs_2_
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ret
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SYM_FUNC_END(xor_regs_2_)
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SYM_FUNC_START(xor_regs_3_)
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vsetvli a4, a0, e8, m8, ta, ma
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vle8.v v0, (a1)
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vle8.v v8, (a2)
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sub a0, a0, a4
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vxor.vv v0, v0, v8
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vle8.v v16, (a3)
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add a2, a2, a4
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vxor.vv v16, v0, v16
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add a3, a3, a4
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vse8.v v16, (a1)
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add a1, a1, a4
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bnez a0, xor_regs_3_
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ret
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SYM_FUNC_END(xor_regs_3_)
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SYM_FUNC_START(xor_regs_4_)
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vsetvli a5, a0, e8, m8, ta, ma
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vle8.v v0, (a1)
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vle8.v v8, (a2)
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sub a0, a0, a5
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vxor.vv v0, v0, v8
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vle8.v v16, (a3)
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add a2, a2, a5
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vxor.vv v0, v0, v16
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vle8.v v24, (a4)
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add a3, a3, a5
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vxor.vv v16, v0, v24
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add a4, a4, a5
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vse8.v v16, (a1)
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add a1, a1, a5
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bnez a0, xor_regs_4_
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ret
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SYM_FUNC_END(xor_regs_4_)
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SYM_FUNC_START(xor_regs_5_)
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vsetvli a6, a0, e8, m8, ta, ma
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vle8.v v0, (a1)
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vle8.v v8, (a2)
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sub a0, a0, a6
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vxor.vv v0, v0, v8
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vle8.v v16, (a3)
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add a2, a2, a6
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vxor.vv v0, v0, v16
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vle8.v v24, (a4)
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add a3, a3, a6
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vxor.vv v0, v0, v24
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vle8.v v8, (a5)
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add a4, a4, a6
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vxor.vv v16, v0, v8
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add a5, a5, a6
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vse8.v v16, (a1)
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add a1, a1, a6
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bnez a0, xor_regs_5_
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ret
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SYM_FUNC_END(xor_regs_5_)
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