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i2c: tegra: Add support for Tegra410

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Add support for the Tegra410 SoC, which has 4 I2C controllers. The
controllers are feature-equivalent to Tegra264; only the register
offsets differ.

Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20260324055843.549808-4-kkartik@nvidia.com
This commit is contained in:
Kartik Rajput 2026-03-24 11:28:43 +05:30 • committed by Andi Shyti
commit 59717f2601
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1 changed files with 63 additions and 0 deletions
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63
drivers/i2c/busses/i2c-tegra.c
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@ -275,6 +275,34 @@ static const struct tegra_i2c_regs tegra264_i2c_regs = {
.sw_mutex = 0x0ec,
};
static const struct tegra_i2c_regs tegra410_i2c_regs = {
.cnfg = 0x000,
.status = 0x01c,
.sl_cnfg = 0x020,
.sl_addr1 = 0x02c,
.sl_addr2 = 0x030,
.tx_fifo = 0x054,
.rx_fifo = 0x058,
.packet_transfer_status = 0x05c,
.fifo_control = 0x060,
.fifo_status = 0x064,
.int_mask = 0x068,
.int_status = 0x06c,
.clk_divisor = 0x070,
.bus_clear_cnfg = 0x088,
.bus_clear_status = 0x08c,
.config_load = 0x090,
.clken_override = 0x094,
.interface_timing_0 = 0x098,
.interface_timing_1 = 0x09c,
.hs_interface_timing_0 = 0x0a0,
.hs_interface_timing_1 = 0x0a4,
.master_reset_cntrl = 0x0ac,
.mst_fifo_control = 0x0b8,
.mst_fifo_status = 0x0bc,
.sw_mutex = 0x0f0,
};
/*
* msg_end_type: The bus control which needs to be sent at end of transfer.
* @MSG_END_STOP: Send stop pulse.
@ -2085,6 +2113,40 @@ static const struct tegra_i2c_hw_feature tegra264_i2c_hw = {
.regs = &tegra264_i2c_regs,
};
static const struct tegra_i2c_hw_feature tegra410_i2c_hw = {
.has_continue_xfer_support = true,
.has_per_pkt_xfer_complete_irq = true,
.clk_divisor_hs_mode = 1,
.clk_divisor_std_mode = 0x3f,
.clk_divisor_fast_mode = 0x2c,
.clk_divisor_fast_plus_mode = 0x11,
.has_config_load_reg = true,
.has_multi_master_mode = true,
.has_slcg_override_reg = true,
.has_mst_fifo = true,
.has_mst_reset = true,
.quirks = &tegra194_i2c_quirks,
.supports_bus_clear = true,
.has_apb_dma = false,
.tlow_std_mode = 0x8,
.thigh_std_mode = 0x7,
.tlow_fast_mode = 0x2,
.thigh_fast_mode = 0x2,
.tlow_fastplus_mode = 0x2,
.thigh_fastplus_mode = 0x2,
.tlow_hs_mode = 0x8,
.thigh_hs_mode = 0x6,
.setup_hold_time_std_mode = 0x08080808,
.setup_hold_time_fast_mode = 0x02020202,
.setup_hold_time_fastplus_mode = 0x02020202,
.setup_hold_time_hs_mode = 0x0b0b0b,
.has_interface_timing_reg = true,
.enable_hs_mode_support = true,
.has_mutex = true,
.variant = TEGRA_I2C_VARIANT_DEFAULT,
.regs = &tegra410_i2c_regs,
};
static const struct of_device_id tegra_i2c_of_match[] = {
{ .compatible = "nvidia,tegra264-i2c", .data = &tegra264_i2c_hw, },
{ .compatible = "nvidia,tegra256-i2c", .data = &tegra256_i2c_hw, },
@ -2395,6 +2457,7 @@ static const struct acpi_device_id tegra_i2c_acpi_match[] = {
{.id = "NVDA0101", .driver_data = (kernel_ulong_t)&tegra210_i2c_hw},
{.id = "NVDA0201", .driver_data = (kernel_ulong_t)&tegra186_i2c_hw},
{.id = "NVDA0301", .driver_data = (kernel_ulong_t)&tegra194_i2c_hw},
{.id = "NVDA2017", .driver_data = (kernel_ulong_t)&tegra410_i2c_hw},
{ }
};
MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match);