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mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode

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As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
During testing it is found that, if the DMA buffer is not aligned to 128
bit it fallback to PIO mode. In such cases, 64-bit access is much more
efficient than the current 16-bit.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250730164618.233117-2-biju.das.jz@bp.renesas.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Biju Das 2025-07-30 17:46:14 +01:00 • committed by Ulf Hansson
commit 74f44ad07d
3 changed files with 51 additions and 0 deletions
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15
drivers/mmc/host/tmio_mmc.h
View file

@ -16,6 +16,7 @@
#include <linux/dmaengine.h>
#include <linux/highmem.h>
#include <linux/io.h>
#include <linux/mutex.h>
#include <linux/pagemap.h>
#include <linux/scatterlist.h>
@ -242,6 +243,20 @@ static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count);
}
#ifdef CONFIG_64BIT
static inline void sd_ctrl_read64_rep(struct tmio_mmc_host *host, int addr,
u64 *buf, int count)
{
readsq(host->ctl + (addr << host->bus_shift), buf, count);
}
static inline void sd_ctrl_write64_rep(struct tmio_mmc_host *host, int addr,
const u64 *buf, int count)
{
writesq(host->ctl + (addr << host->bus_shift), buf, count);
}
#endif
static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
u16 val)
{

33
drivers/mmc/host/tmio_mmc_core.c
View file

@ -349,6 +349,39 @@ static void tmio_mmc_transfer_data(struct tmio_mmc_host *host,
/*
* Transfer the data
*/
#ifdef CONFIG_64BIT
if (host->pdata->flags & TMIO_MMC_64BIT_DATA_PORT) {
u64 *buf64 = (u64 *)buf;
u64 data = 0;
if (count >= 8) {
if (is_read)
sd_ctrl_read64_rep(host, CTL_SD_DATA_PORT,
buf64, count >> 3);
else
sd_ctrl_write64_rep(host, CTL_SD_DATA_PORT,
buf64, count >> 3);
}
/* if count was multiple of 8 */
if (!(count & 0x7))
return;
buf64 += count >> 3;
count %= 8;
if (is_read) {
sd_ctrl_read64_rep(host, CTL_SD_DATA_PORT, &data, 1);
memcpy(buf64, &data, count);
} else {
memcpy(&data, buf64, count);
sd_ctrl_write64_rep(host, CTL_SD_DATA_PORT, &data, 1);
}
return;
}
#endif
if (host->pdata->flags & TMIO_MMC_32BIT_DATA_PORT) {
u32 data = 0;
u32 *buf32 = (u32 *)buf;

3
include/linux/platform_data/tmio.h
View file

@ -47,6 +47,9 @@
/* Some controllers have a CBSY bit */
#define TMIO_MMC_HAVE_CBSY BIT(11)
/* Some controllers have a 64-bit wide data port register */
#define TMIO_MMC_64BIT_DATA_PORT BIT(12)
struct tmio_mmc_data {
void *chan_priv_tx;
void *chan_priv_rx;