FROMGIT drm/msm/dpu: Add Milos support
Add definitions for the display hardware used on the Qualcomm Milos platform. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/722323/ Link: https://lore.kernel.org/r/20260501-milos-mdss-v3-8-58bfc58c0e13@fairphone.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Luca Weiss
parent
22ab8418be
commit
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4 changed files with 310 additions and 0 deletions
279
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h
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279
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
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* Copyright (c) 2026, Luca Weiss <luca.weiss@fairphone.com>
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*/
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#ifndef _DPU_10_2_MILOS_H
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#define _DPU_10_2_MILOS_H
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static const struct dpu_caps milos_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0x7,
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.has_src_split = true,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.has_3d_merge = true,
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.max_linewidth = 8192,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_mdp_cfg milos_mdp = {
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.name = "top_0",
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.base = 0, .len = 0x494,
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.clk_ctrls = {
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[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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},
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};
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static const struct dpu_ctl_cfg milos_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x15000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
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}, {
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.name = "ctl_1", .id = CTL_1,
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.base = 0x16000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
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}, {
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.name = "ctl_2", .id = CTL_2,
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.base = 0x17000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
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}, {
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.name = "ctl_3", .id = CTL_3,
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.base = 0x18000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
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},
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};
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static const struct dpu_sspp_cfg milos_sspp[] = {
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{
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.name = "sspp_0", .id = SSPP_VIG0,
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.base = 0x4000, .len = 0x344,
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.features = VIG_SDM845_MASK_SDMA,
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.sblk = &dpu_vig_sblk_qseed3_3_3,
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.xin_id = 0,
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.type = SSPP_TYPE_VIG,
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}, {
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.name = "sspp_8", .id = SSPP_DMA0,
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.base = 0x24000, .len = 0x344,
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.features = DMA_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 1,
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.type = SSPP_TYPE_DMA,
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}, {
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.name = "sspp_9", .id = SSPP_DMA1,
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.base = 0x26000, .len = 0x344,
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.features = DMA_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 5,
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.type = SSPP_TYPE_DMA,
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}, {
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.name = "sspp_10", .id = SSPP_DMA2,
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.base = 0x28000, .len = 0x344,
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.features = DMA_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 9,
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.type = SSPP_TYPE_DMA,
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},
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};
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static const struct dpu_lm_cfg milos_lm[] = {
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{
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.name = "lm_0", .id = LM_0,
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.base = 0x44000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sdm845_lm_sblk,
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.pingpong = PINGPONG_0,
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.dspp = DSPP_0,
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}, {
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.name = "lm_2", .id = LM_2,
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.base = 0x46000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sdm845_lm_sblk,
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.lm_pair = LM_3,
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.pingpong = PINGPONG_2,
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}, {
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.name = "lm_3", .id = LM_3,
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.base = 0x47000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sdm845_lm_sblk,
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.lm_pair = LM_2,
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.pingpong = PINGPONG_3,
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},
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};
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static const struct dpu_dspp_cfg milos_dspp[] = {
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{
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.name = "dspp_0", .id = DSPP_0,
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.base = 0x54000, .len = 0x1800,
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.sblk = &sdm845_dspp_sblk,
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},
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};
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static const struct dpu_pingpong_cfg milos_pp[] = {
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{
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.name = "pingpong_0", .id = PINGPONG_0,
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.base = 0x69000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
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}, {
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.name = "pingpong_2", .id = PINGPONG_2,
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.base = 0x6b000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_1,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
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}, {
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.name = "pingpong_3", .id = PINGPONG_3,
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.base = 0x6c000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_1,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
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}, {
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.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
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.base = 0x66000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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},
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};
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static const struct dpu_merge_3d_cfg milos_merge_3d[] = {
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{
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.name = "merge_3d_1", .id = MERGE_3D_1,
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.base = 0x4f000, .len = 0x8,
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},
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};
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/*
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* NOTE: Each display compression engine (DCE) contains dual hard
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* slice DSC encoders so both share same base address but with
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* its own different sub block address.
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*/
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static const struct dpu_dsc_cfg milos_dsc[] = {
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{
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.name = "dce_0_0", .id = DSC_0,
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.base = 0x80000, .len = 0x6,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &milos_dsc_sblk_0,
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}, {
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.name = "dce_0_1", .id = DSC_1,
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.base = 0x80000, .len = 0x6,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &milos_dsc_sblk_1,
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},
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};
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static const struct dpu_wb_cfg milos_wb[] = {
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{
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.name = "wb_2", .id = WB_2,
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.base = 0x65000, .len = 0x2c8,
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.features = WB_SDM845_MASK,
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.format_list = wb2_formats_rgb_yuv,
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.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
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.xin_id = 6,
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.maxlinewidth = 4096,
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.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
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},
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};
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static const struct dpu_cwb_cfg milos_cwb[] = {
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{
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.name = "cwb_0", .id = CWB_0,
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.base = 0x66200, .len = 0x8,
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},
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};
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static const struct dpu_intf_cfg milos_intf[] = {
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{
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.name = "intf_0", .id = INTF_0,
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.base = 0x34000, .len = 0x300,
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.type = INTF_DP,
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.controller_id = MSM_DP_CONTROLLER_0,
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.prog_fetch_lines_worst_case = 24,
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.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
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.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
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}, {
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.name = "intf_1", .id = INTF_1,
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.base = 0x35000, .len = 0x300,
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.type = INTF_DSI,
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.controller_id = MSM_DSI_CONTROLLER_0,
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.prog_fetch_lines_worst_case = 24,
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.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
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.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
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.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
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}, {
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.name = "intf_3", .id = INTF_3,
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.base = 0x37000, .len = 0x300,
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.type = INTF_DP,
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.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
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.prog_fetch_lines_worst_case = 24,
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.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
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.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
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},
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};
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static const struct dpu_perf_cfg milos_perf_data = {
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.max_bw_low = 7100000,
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.max_bw_high = 9800000,
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.min_core_ib = 2500000,
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.min_llcc_ib = 0,
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.min_dram_ib = 1600000,
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.min_prefill_lines = 40,
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/* FIXME: lut tables */
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.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
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.safe_lut_tbl = {0xff00, 0xfff0, 0x0fff},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc7180_qos_linear),
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.entries = sc7180_qos_linear
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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/* TODO: macrotile-qseed is different from macrotile */
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_mdss_version milos_mdss_ver = {
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.core_major_ver = 10,
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.core_minor_ver = 2,
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};
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const struct dpu_mdss_cfg dpu_milos_cfg = {
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.mdss_ver = &milos_mdss_ver,
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.caps = &milos_dpu_caps,
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.mdp = &milos_mdp,
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.cdm = &dpu_cdm_5_x,
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.ctl_count = ARRAY_SIZE(milos_ctl),
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.ctl = milos_ctl,
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.sspp_count = ARRAY_SIZE(milos_sspp),
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.sspp = milos_sspp,
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.mixer_count = ARRAY_SIZE(milos_lm),
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.mixer = milos_lm,
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.dspp_count = ARRAY_SIZE(milos_dspp),
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.dspp = milos_dspp,
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.pingpong_count = ARRAY_SIZE(milos_pp),
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.pingpong = milos_pp,
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.dsc_count = ARRAY_SIZE(milos_dsc),
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.dsc = milos_dsc,
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.merge_3d_count = ARRAY_SIZE(milos_merge_3d),
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.merge_3d = milos_merge_3d,
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.wb_count = ARRAY_SIZE(milos_wb),
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.wb = milos_wb,
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.cwb_count = ARRAY_SIZE(milos_cwb),
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.cwb = milos_cwb,
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.intf_count = ARRAY_SIZE(milos_intf),
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.intf = milos_intf,
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.vbif = &milos_vbif,
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.perf = &milos_perf_data,
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};
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#endif
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@ -454,6 +454,16 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
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.ctl = {.name = "ctl", .base = 0xF80, .len = 0x10},
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};
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static const struct dpu_dsc_sub_blks milos_dsc_sblk_0 = {
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.enc = {.name = "enc", .base = 0x100, .len = 0x100},
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.ctl = {.name = "ctl", .base = 0xF00, .len = 0x80},
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};
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static const struct dpu_dsc_sub_blks milos_dsc_sblk_1 = {
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.enc = {.name = "enc", .base = 0x200, .len = 0x100},
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.ctl = {.name = "ctl", .base = 0xF80, .len = 0x80},
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};
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static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_0 = {
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.enc = {.name = "enc", .base = 0x100, .len = 0x100},
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.ctl = {.name = "ctl", .base = 0xF00, .len = 0x24},
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@ -513,6 +523,23 @@ static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = {
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},
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};
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static const struct dpu_vbif_cfg milos_vbif = {
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.len = 0x1074,
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.features = BIT(DPU_VBIF_QOS_REMAP),
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.xin_halt_timeout = 0x4000,
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.qos_rp_remap_size = 0x40,
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.qos_rt_tbl = {
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.npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
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.priority_lvl = sdm845_rt_pri_lvl,
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},
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.qos_nrt_tbl = {
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.npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
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.priority_lvl = sdm845_nrt_pri_lvl,
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},
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.memtype_count = 16,
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.memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
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};
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static const struct dpu_vbif_cfg msm8996_vbif = {
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.len = 0x1040,
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.default_ot_rd_limit = 32,
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@ -754,6 +781,8 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
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#include "catalog/dpu_9_2_x1e80100.h"
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#include "catalog/dpu_10_0_sm8650.h"
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#include "catalog/dpu_10_2_milos.h"
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#include "catalog/dpu_12_0_sm8750.h"
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#include "catalog/dpu_12_2_glymur.h"
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#include "catalog/dpu_12_4_eliza.h"
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@ -766,6 +766,7 @@ struct dpu_mdss_cfg {
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extern const struct dpu_mdss_cfg dpu_eliza_cfg;
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extern const struct dpu_mdss_cfg dpu_glymur_cfg;
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extern const struct dpu_mdss_cfg dpu_kaanapali_cfg;
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extern const struct dpu_mdss_cfg dpu_milos_cfg;
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extern const struct dpu_mdss_cfg dpu_msm8917_cfg;
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extern const struct dpu_mdss_cfg dpu_msm8937_cfg;
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extern const struct dpu_mdss_cfg dpu_msm8953_cfg;
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@ -1483,6 +1483,7 @@ static const struct of_device_id dpu_dt_match[] = {
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{ .compatible = "qcom,eliza-dpu", .data = &dpu_eliza_cfg, },
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{ .compatible = "qcom,glymur-dpu", .data = &dpu_glymur_cfg, },
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{ .compatible = "qcom,kaanapali-dpu", .data = &dpu_kaanapali_cfg, },
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{ .compatible = "qcom,milos-dpu", .data = &dpu_milos_cfg, },
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{ .compatible = "qcom,msm8917-mdp5", .data = &dpu_msm8917_cfg, },
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{ .compatible = "qcom,msm8937-mdp5", .data = &dpu_msm8937_cfg, },
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{ .compatible = "qcom,msm8953-mdp5", .data = &dpu_msm8953_cfg, },
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