ASoC: qcom: q6apm-lpass-dais: Add MI2S clock control
Add support for MI2S clock control within q6apm-lpass DAIs, including handling of MCLK, BCLK, and ECLK via the DAI .set_sysclk callback. Each MI2S port now retrieves its clock handles from the device tree, allowing per-port clock configuration and proper enable/disable during startup and shutdown. Co-developed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
This commit is contained in:
Mohammad Rafi Shaik
parent
0df93b3ece
commit
f930864a7c
2 changed files with 156 additions and 2 deletions
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@ -2,10 +2,12 @@
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// Copyright (c) 2021, Linaro Limited
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#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <sound/pcm.h>
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@ -15,13 +17,22 @@
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#include "q6dsp-common.h"
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#include "audioreach.h"
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#include "q6apm.h"
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#include "q6prm.h"
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#define AUDIOREACH_BE_PCM_BASE 16
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struct q6apm_dai_priv_data {
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struct clk *mclk;
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struct clk *bclk;
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struct clk *eclk;
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bool mclk_enabled, bclk_enabled, eclk_enabled;
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};
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struct q6apm_lpass_dai_data {
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struct q6apm_graph *graph[APM_PORT_MAX];
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bool is_port_started[APM_PORT_MAX];
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struct audioreach_module_config module_config[APM_PORT_MAX];
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struct q6apm_dai_priv_data priv[APM_PORT_MAX];
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};
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static int q6dma_set_channel_map(struct snd_soc_dai *dai,
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@ -251,6 +262,73 @@ static int q6apm_lpass_dai_startup(struct snd_pcm_substream *substream, struct s
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return 0;
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}
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static int q6i2s_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
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{
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return q6apm_lpass_dai_startup(substream, dai);
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}
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static void q6i2s_lpass_dai_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
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{
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struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
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if (dai_data->priv[dai->id].mclk_enabled) {
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clk_disable_unprepare(dai_data->priv[dai->id].mclk);
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dai_data->priv[dai->id].mclk_enabled = false;
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}
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if (dai_data->priv[dai->id].bclk_enabled) {
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clk_disable_unprepare(dai_data->priv[dai->id].bclk);
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dai_data->priv[dai->id].bclk_enabled = false;
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}
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if (dai_data->priv[dai->id].eclk_enabled) {
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clk_disable_unprepare(dai_data->priv[dai->id].eclk);
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dai_data->priv[dai->id].eclk_enabled = false;
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}
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q6apm_lpass_dai_shutdown(substream, dai);
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}
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static int q6i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, unsigned int freq, int dir)
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{
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struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
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struct clk *sysclk = NULL;
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bool *enabled = NULL;
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int ret = 0;
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switch (clk_id) {
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case LPAIF_MI2S_MCLK:
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sysclk = dai_data->priv[dai->id].mclk;
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enabled = &dai_data->priv[dai->id].mclk_enabled;
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break;
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case LPAIF_MI2S_BCLK:
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sysclk = dai_data->priv[dai->id].bclk;
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enabled = &dai_data->priv[dai->id].bclk_enabled;
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break;
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case LPAIF_MI2S_ECLK:
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sysclk = dai_data->priv[dai->id].eclk;
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enabled = &dai_data->priv[dai->id].eclk_enabled;
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break;
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default:
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return -EINVAL;
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}
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if (sysclk) {
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if (*enabled)
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return 0;
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clk_set_rate(sysclk, freq);
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ret = clk_prepare_enable(sysclk);
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if (ret) {
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dev_err(dai->dev, "Error, Unable to prepare (%d) sysclk\n", clk_id);
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return ret;
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}
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*enabled = true;
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}
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return ret;
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}
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static int q6i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev);
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@ -272,11 +350,12 @@ static const struct snd_soc_dai_ops q6dma_ops = {
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static const struct snd_soc_dai_ops q6i2s_ops = {
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.prepare = q6apm_lpass_dai_prepare,
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.startup = q6apm_lpass_dai_startup,
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.shutdown = q6apm_lpass_dai_shutdown,
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.startup = q6i2s_dai_startup,
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.shutdown = q6i2s_lpass_dai_shutdown,
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.set_channel_map = q6dma_set_channel_map,
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.hw_params = q6dma_hw_params,
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.set_fmt = q6i2s_set_fmt,
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.set_sysclk = q6i2s_set_sysclk,
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.trigger = q6apm_lpass_dai_trigger,
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};
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@ -297,6 +376,73 @@ static const struct snd_soc_component_driver q6apm_lpass_dai_component = {
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.remove_order = SND_SOC_COMP_ORDER_FIRST,
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};
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static int of_q6apm_parse_dai_data(struct device *dev,
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struct q6apm_lpass_dai_data *data)
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{
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int ret;
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for_each_child_of_node_scoped(dev->of_node, node) {
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struct q6apm_dai_priv_data *priv;
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int id;
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ret = of_property_read_u32(node, "reg", &id);
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if (ret || id < 0 || id >= APM_PORT_MAX) {
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dev_err(dev, "valid dai id not found:%d\n", ret);
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continue;
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}
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switch (id) {
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/* MI2S specific properties */
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case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX:
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case QUINARY_MI2S_RX ... QUINARY_MI2S_TX:
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case SENARY_MI2S_RX ... SENARY_MI2S_TX:
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priv = &data->priv[id];
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priv->mclk = of_clk_get_by_name(node, "mclk");
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if (IS_ERR(priv->mclk)) {
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if (PTR_ERR(priv->mclk) == -EPROBE_DEFER)
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return dev_err_probe(dev, PTR_ERR(priv->mclk),
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"unable to get mi2s mclk\n");
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priv->mclk = NULL;
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}
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priv->bclk = of_clk_get_by_name(node, "bclk");
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if (IS_ERR(priv->bclk)) {
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if (PTR_ERR(priv->bclk) == -EPROBE_DEFER) {
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if (priv->mclk) {
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clk_put(priv->mclk);
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priv->mclk = NULL;
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}
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return dev_err_probe(dev, PTR_ERR(priv->bclk),
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"unable to get mi2s bclk\n");
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}
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priv->bclk = NULL;
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}
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priv->eclk = of_clk_get_by_name(node, "eclk");
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if (IS_ERR(priv->eclk)) {
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if (PTR_ERR(priv->eclk) == -EPROBE_DEFER) {
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if (priv->mclk) {
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clk_put(priv->mclk);
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priv->mclk = NULL;
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}
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if (priv->bclk) {
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clk_put(priv->bclk);
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priv->bclk = NULL;
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}
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return dev_err_probe(dev, PTR_ERR(priv->eclk),
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"unable to get mi2s eclk\n");
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}
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priv->eclk = NULL;
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}
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break;
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default:
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break;
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}
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}
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return 0;
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}
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static int q6apm_lpass_dai_dev_probe(struct platform_device *pdev)
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{
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struct q6dsp_audio_port_dai_driver_config cfg;
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@ -304,12 +450,16 @@ static int q6apm_lpass_dai_dev_probe(struct platform_device *pdev)
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struct snd_soc_dai_driver *dais;
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struct device *dev = &pdev->dev;
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int num_dais;
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int ret;
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dai_data = devm_kzalloc(dev, sizeof(*dai_data), GFP_KERNEL);
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if (!dai_data)
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return -ENOMEM;
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dev_set_drvdata(dev, dai_data);
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ret = of_q6apm_parse_dai_data(dev, dai_data);
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if (ret)
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return ret;
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memset(&cfg, 0, sizeof(cfg));
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cfg.q6i2s_ops = &q6i2s_ops;
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@ -3,6 +3,10 @@
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#ifndef __Q6PRM_H__
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#define __Q6PRM_H__
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#define LPAIF_MI2S_MCLK 1
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#define LPAIF_MI2S_BCLK 2
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#define LPAIF_MI2S_ECLK 3
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/* Clock ID for Primary I2S IBIT */
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#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
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/* Clock ID for Primary I2S EBIT */
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