e27264daac
The DT bindings for inline-crypto engine do not specify the UFS_PHY_GDSC power-domain and iface clock. Without enabling the iface clock and the associated power-domain the ICE hardware cannot function correctly and leads to unclocked hardware accesses being observed during probe. Fix the DT bindings for inline-crypto engine to require the UFS_PHY_GDSC power-domain and iface clock for new devices (Eliza and Milos) introduced in the current release (7.1) with yet-to-stabilize ABI, while preserving backward compatibility for older devices. Fixes:618195a7ac("dt-bindings: crypto: qcom,inline-crypto-engine: Document the Eliza ICE") Fixes:85faec1e85("dt-bindings: crypto: qcom,inline-crypto-engine: document the Milos ICE") Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-1-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
111 lines
2.5 KiB
YAML
111 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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properties:
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compatible:
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items:
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- enum:
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- qcom,eliza-inline-crypto-engine
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- qcom,kaanapali-inline-crypto-engine
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- qcom,milos-inline-crypto-engine
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- qcom,qcs8300-inline-crypto-engine
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- qcom,sa8775p-inline-crypto-engine
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- qcom,sc7180-inline-crypto-engine
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- qcom,sc7280-inline-crypto-engine
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- qcom,sm8450-inline-crypto-engine
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- qcom,sm8550-inline-crypto-engine
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- qcom,sm8650-inline-crypto-engine
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- qcom,sm8750-inline-crypto-engine
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- const: qcom,inline-crypto-engine
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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items:
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- const: core
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- const: iface
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power-domains:
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maxItems: 1
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operating-points-v2: true
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opp-table:
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type: object
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required:
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- compatible
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- reg
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- clocks
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,eliza-inline-crypto-engine
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- qcom,milos-inline-crypto-engine
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then:
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required:
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- power-domains
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- clock-names
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properties:
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clocks:
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minItems: 2
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clock-names:
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minItems: 2
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examples:
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- |
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#include <dt-bindings/clock/qcom,sm8550-gcc.h>
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crypto@1d88000 {
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compatible = "qcom,sm8550-inline-crypto-engine",
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"qcom,inline-crypto-engine";
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reg = <0x01d88000 0x8000>;
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clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>;
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clock-names = "core",
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"iface";
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power-domains = <&gcc UFS_PHY_GDSC>;
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operating-points-v2 = <&ice_opp_table>;
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ice_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-201500000 {
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opp-hz = /bits/ 64 <201500000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-403000000 {
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opp-hz = /bits/ 64 <403000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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...
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