ARM NEON
NEON backend for VectorF32 on AArch64: one float32x4_t per vector (Len * Packing <= 4), with a vectorised sin/cos port of the SSE helpers. VectorF16 gets a native float16x8_t path when the target has ARMv8.2-FP16 arithmetic. Without it VectorF16 aliases VectorF32, which converts fp16 <-> fp32 on Load/Store. The scalar fallback gains the batched Dot that MatrixRowMajor relies on. Test tiers added for armv8-a and armv8.2-a+fp16. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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6 changed files with 825 additions and 17 deletions
10
project.cpp
10
project.cpp
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@ -46,12 +46,22 @@ extern "C" Configuration CrafterBuildProject(std::span<const std::string_view> a
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{"rv64gcv", "generic"},
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}};
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// AArch64 has a single NEON register width (128-bit), so the tiers
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// differ in VectorF16 only: ARMv8.2-FP16 gives it a native half-precision
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// path, the baseline aliases it to VectorF32.
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std::array<MarchTier, 2> armTiers = {{
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{"armv8.2-a+fp16", "generic"},
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{"armv8-a", "generic"},
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}};
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const std::string_view target = cfg.target;
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const bool isX86 = target.starts_with("x86_64") || target.starts_with("i686");
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const bool isRiscv = target.starts_with("riscv");
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const bool isArm = target.starts_with("aarch64");
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for (std::string_view name : { "Vector", "Intersection", "Matrix" }) {
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if (isX86) cfg.AddMarchVariants(name, mathInterfaces, x86Tiers);
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if (isRiscv) cfg.AddMarchVariants(name, mathInterfaces, riscvTiers);
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if (isArm) cfg.AddMarchVariants(name, mathInterfaces, armTiers);
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}
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return cfg;
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